The present invention relates to a semiconductor memory device; and, more particularly, to a data output circuit in a semiconductor memory device.
In a system equipped with a plurality of semiconductor devices for performing various functions, a semiconductor memory device functions as an apparatus for storing data. The semiconductor memory device outputs data, which correspond to the address signals inputted from a data processing unit, for example, a central processing unit, to a device to request the data, or stores data delivered by the data processing unit in unit cells corresponding to the address signals which are inputted together with the data.
The operating speed of the system is getting faster and faster. Therefore, the semiconductor memory devices are more and more required to have fast input and output speed in the data processing unit. Recently, the operating speed of the data processing unit is getting faster and faster in the engineering development process of the semiconductor integrated circuits; however, the semiconductor memory devices to deliver the data to the data processing unit is not in compliance with the input and output speed of the data processing unit.
In order to enhance the data I/O speed of the semiconductor memory device to a degree which is satisfied by the data processing unit, various semiconductor memory devices have been developed up to now. Synchronous memory devices in which the data are inputted and outputted in response to system clock signals have been proposed until a recent date. The synchronous memory devices output the data to the data processing unit in response to the inputted system clock signals and also receive the data from the data processing unit in response to the inputted system clock signals. However, since the synchronous memory devices are unable to follow the operating speed of the data processing unit, DDR synchronous memory devices have been developed. The DDR synchronous memory devices input and output the data in response to a transition timing of the system clock signal. That is, in the DDR synchronous memory devices, the data are inputted and outputted in synchronization with rising and falling edges of the system clock signal.
However, the system clock signal inputted into the semiconductor memory device reaches to a data output circuit, inevitably having a delay time which is caused by both a clock input buffer disposed within the memory device and a transmission line to transmit the clock signal thereto. Therefore, when the data output circuit outputs the data in synchronization with the system clock signals which already have such a delay time, an external circuit which receives the output data from the semiconductor memory device may take them asynchronously with the rising edge and the falling edge of the system clock signal.
To solve this problem, the semiconductor memory device includes a delay locked loop circuit for locking an amount of the delay time of the clock signal. The delay locked loop circuit is a circuit to compensate for the delay time which is caused by the internal circuits in the memory device until the system clock signal is delivered to the data output circuit after being inputted to the memory device. The delay locked loop circuit finds out an amount of the delay time of the system clock signal which is caused by delay circuits, such as the input buffer and the clock signal transmission line, and delays the system clock signal based on the amount of delay which has been found. The delay locked loop outputs the delayed system clock to the data output circuit. That is, the system clock signal inputted into the memory device is delivered to the data output circuit with a fixed delay time by the delay locked loop. The data output circuit outputs the data in synchronization with the delay-locked clock signal and the external circuit regards the output data as the normal data which are accurately outputted in synchronization with the system clock signal.
In the actual operation, the delay-locked clock signal outputted from the delay locked loop circuit is transferred to an output buffer at a point of time which is determined faster than the data output time by one period of time and the data are outputted in synchronization with the transferred delay-locked clock signal. As a result, the data are more rapidly outputted than the amount of delay time of the system clock signals caused by the internal circuits of the memory device. In this way, it seems to the external circuit of the memory device that the data are accurately outputted in synchronization with the rising edge and the falling edge of the system clock signal. In conclusion, the delay locked loop circuit is a circuit to find out a delay value to compensate for the delay time of the system clock signal within the memory device, thereby achieving the fast data output operation.
The semiconductor memory devices output the data to an external circuit in synchronization with the delay locked clock signals after internally preparing the data to be outputted using the delay locked clock signals from the delay locked loop circuit. Generally, the timing relation between the transition timing of the system clock signal and the output timing of the data is expressed as “tAC.” Accordingly, in order to control “tAC,” the semiconductor memory devices should control the output timing of the delay locked clock signal. However, this causes a mismatch of a timing required to process the data to be outputted therein. As a result, there is a problem in that the data are not outputted at a predetermined timing.